February 10, 2014
San Jose, CA USA
This workshop focused on the challenges of next generation electrical link technology to support 400G standards in anticipation that 400 Gb/s interfaces will require denser electrical links than current 28 Gb/s serial link technology. Speakers presented on the chip-to-module and intra-rack / backplane applications that are outlined in the OIF’s “Next Generation Interconnect Framework” project. The project provides an overall picture of the application spaces and identifies technological challenges for next generation interconnects throughout a system.


8:30am – 9:00am Continental Breakfast and Badge Pick-Up
9:00am – 10:00am Session 1: CEI History and Progress

  • David Stauffer, OIF PLL Working Group Chair and Board Member, Kandou

Title: CEI History and ChallengesAbstract: A brief history of CEI was presented including a roadmap to CEI-25G variants. CEI-56G project overview and key challenges for the next generation of CEI to support 400G interfaces are discussed.

  • Tom Palkert, OIF PLL Working Group Vice Chair – Electrical, Molex
10:00am – 10:15am Coffee Break
10:15am – 12:00pm Session 2: CEI-56G-VSR Chip-to-Module Interface Requirements

  • Scott Kipp, Brocade

Title: 56G System Vendors RequirementsAbstract:This presentation explored the relationship between making faster, higher port-count ASICs and optics as the industry doubles the data rate from 28Gb/s to 56Gb/s. As Moore’s Law enables more ports to be packed on individual switch ASICs, the industry needs higher density solutions than SEP+ and even QSFP+ enable. Deployments of embedded optics will be needed to keep pace with the ASICs that can deliver over 100 ports in a single chip. This presentation looked at several deployment possibilities for 10GbE, 32GFC, 40GbE, 64GFC, 100GbE, 128GFC, 256GFC, and 400GbE.

  • Chris Cole, Finisar

Title: Optics Considerations in Developing Next Generation 400Gb/s Electrical SpecificationsAbstract: The OIF has approved CEI-56G-VSR Project for chip-to-module applications and is discussing starting CEI-56G-MR Project for chip-to-chip applications. There are many direct electrical design considerations that drive the specifications, which are covered by other speakers. Additionally, for optimal system partitioning optics constraints also have to be factored into the electrical design. These include front panel pluggable and board mounted optics, 40Gb/s per lane 40G optics, Nx50Gb/s per lane 100G and 400G optics, and Mx100G per lane 100G and 400G optics.

  • Gary Nicholl, Cisco
12:00pm – 1:30pm Lunch provided
1:30pm – 3:15pm Session 3: CEI-56G-VSR Chip-to-Module Technologies

  • Adam Healey, LSI

Title: Modulation, Equalization, and Forward Error Correction for a 56 Gb/s Chip-to-Module LinkAbstract: A number of factors influence the choice of modulation and equalization for chip-to-module links operating at data rates up to 56 Gb/s per lane. These factors include the signal integrity delivered by the electrical channel, the performance of electrical circuits at high speed, and the use of Forward Error Correction to improve the performance of the end-to-end link. These factors were explored and data presented to motivate likely chip-to-module link architectures.

  • Mike Li, Altera

Title: An Investigation of CEI-56G Chip-to-Module and Chip-to-Chip Electrical LinksAbstract: We present our study on the CEI next generation 56 Gbps chip-to-module and chip-to-chip electrical links. The study explores and evaluates the needed characteristics of transmitter (TX), receiver (RX), channel, and modulation schemes in order to meet various channel loss and BER (e.g., 1e-15) objectives. Corresponding modeling and simulation results are presented.

  • Ed Frlan, Semtech and OIF PLL Interoperability WG Chair

Title: Feasibility of PAM-4 Multilevel Signalling for Next Generation CEI-56G-VSR Chip-to-Module InterfacesAbstract: CEI-56G-VSR is expected to become a key specification for next-generation 400G networks by enabling modules with higher density 8x 56G electrical interfaces. Signal integrity issues at the new 56 Gb/s speed node will need to be carefully managed in order to ensure that desired performance targets are met. In addition, this new interface will need to provide the proper balance between cost, technology and power in order to ensure its success in the marketplace. This presentation discussed the feasibility of an electrical PAM-4 based multilevel modulation scheme as an alternative to traditional NRZ based signaling highlighting the expected performance of typical channels in the presence of system noise sources and as well will outline how such a modulation scheme can not only meet demanding signal integrity requirements but also how it positively affects several other factors required in selecting a suitable modulation scheme.

3:15pm – 3:30pm Coffee Break
3:30pm – 6:00pm Session 4: 56G Backplane Requirements and Challenges

  • Joel Goergen, Cisco
  • Brian Holden, Kandou and OIF MA&E Co-Chair – PLL

Title: Modulation options for 400 Gb/s generation backplanes.Abstract: This presentation reviewed the signal modulation options that are available for the 400 Gb/s generation backplanes. Those options include NRZ, PAM-3, PAM-4, PAM-8, 16-QAM, ENRZ, and ENRZ-plus-PAM-3. Several of these have additional coding options to optimize for specific properties. The impact of these modulation choices on the available equalization techniques, notably decision feedback equalization, was also be addressed.

  • Mike Tryson, TE Connectivity

Title: Optical Backplane- Enabler to MultiTerabit SolutionsAbstract: A overview of some of the factors that system developers are experience that are driving (re)-evaluation of optical backplane technology for next generations of systems and platforms. While many examples of optical backplane interconnect system exist, broad market adoption remains low due to a number of fundamental challenges. Will explore the key barriers to adoption and discuss technology insertions that may help overcome many of the barriers.

6:00pm – 7:30pm Reception (hosted by OIF)