Physical and Link Layer Working Group/Physical Layer User Group Working Group

Networking & Operations Working Group/ Network Operator Working Group

NOTE:  For completed OIF technical work and approved Implementation Agreements and/or White Papers, please click here.

To contact a Working Group Chair or Vice Chair, please send an email to technicalquestions@oiforum.com

Physical and Link Layer Working Group/Physical Layer User Group Working Group

  • Common Electrical I/O-224G-Linear (CEI-224G-Linear)
    The CEI-224G-Linear project builds on the approach of CEI-112G-Linear in terms of specification methodology. It will support 224G full linear optical modules for next-gen applications (e.g., Ethernet, Ultra Ethernet Consortium (UEC), Artificial Intelligence/Machine Learning [AI/ML]) with low power, cost/complexity and latency. The TP1/TP1a and TP4/TP4a electrical specifications will enable up to 224G full linear optical modules for Linear Pluggable Optics (LPO), co-packaged optics (CPO) and Near Package Optics (NPO), supporting next-generation low power, low cost and low latency applications. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • 224G PAM4 Protocol Agnostic Link Training
    The 224G PAM4 protocol agnostic link training will define communication method, messaging format and contents, training patterns, states and sequences, diagnostics and fault handling, etc. for link training of a 224G PAM4 class electrical link. The objective is to enhance overall link performance, a critical factor, particularly under challenging conditions, to establish a functional connection. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Common Electrical I/O-224G-XSR Common Electrical on-Package Interface Project (CEI-224G-XSR)
    This project proposes a CEI-224G-XSR project which will develop IA specifications for die-to- die (D2D) and die-to-OE (D2OE) electrical I/O interfaces which can be used to support Nx224G I/O links with significantly reduced power, complexity, and enhanced throughput density. The reach objective shall be at least 50 mm over organic package substrate or other advanced materials. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Common Electrical I/O-224G-VSR-Common Electrical Chip-to-Module Interface Project (CEI-224G-VSR)
    This project proposes a CEI-224G-VSR project which will develop IA specifications for chip-to- module (c2m) interface which can be used to support applications of Nx224G with optimized power, complexity, and enhanced density. The reach objective shall be at least 200 mm host channel, 20 mm module channel and up to one connector over advanced materials. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Common Electrical I/O-224G-MR Common Electrical Chip-to-Chip Interface Project (CEI-224G-MR)
    This project proposes a CEI-224G-MR project which will develop IA specifications for chip- to-chip (c2c) interface which can be used to support applications of Nx224G with reduced power, complexity, and enhanced density. The reach objective shall be at least 500 mm with up to one connector over advanced materials. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Common Electrical I/O-224G-LR Common Electrical Backplane and Copper Cable Interface Project (CEI-224G-LR)
    This project proposes a CEI-224G-LR project which will develop IA specifications for an interface which can be used to support Nx224G over backplane. The reach objective shall be at least 1000 mm with up to two connectors over advanced materials. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Common Electrical I/O-112G Linear (CEI-112G Linear)
    The CEI-112G-LINEAR project defines interface and interconnect requirements for a linear Chip-to-Optical Engine interface to enable low power, low cost, small form factor 112G serial optical modules in CPO, NPO and server/GPU applications. Data lanes are defined to support up to 112 Gbps over advanced material PCBs, package substrates and intra-box cabled interconnects for chip-to-optical engine/module interfaces. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Adding CMIS Support for Host-Module Link Training
    This project provides an optional out of band, protocol agnostic, management mechanism for optimizing link and tuning.   Potential use cases may include OIF CEI 112G, IEEE802.3ck, 128 GFC, IB, XSR+, CEI-224G and other standards.  OB link training based on CMIS will be referred to as CMIS-LT collectively.  For more information, contact Ian Alderdice or Gary Nicholl, Physical and Link Layer Working Group Management Co-Vice Chairs.
  • Enhanced SGMII Electrical Specifications This project leverages the legacy SGMII specifications based on LVDS signaling to define a new E-SGMII specifications based on modernized CML signaling.
    E-SGMII is targeted for high speed 1 GbE (1.25 GBd with 8B/10B) packetized management of optical modules.  E-SGMII is a chip-to-module specifications based on differential AC coupled CML signaling.
    The specifications will define compliance test points and will define an informative channel up to 400 mm long. For more information contact Dave Stauffer, Physical and Link Layer Working Group Chair.
  • Energy Efficient Interfaces
    The Energy Efficient Interfaces Framework project is studying end-user requirements and identifying energy efficient, low latency electrical and optical interfaces necessary to support the future application requirements for AI in the data center. These interfaces include electrical and optical interfaces for co-packaged, near-packaged, and for pluggables and includes retimed, transmit retimed and linear interfaces.   For more information, contact Jeff Hutchins, Physical and Link Layer Working Group EEI Vice Chair.
  • Retimed Tx Linear Rx (RTLR) The RTLR project addresses energy efficiency and low latency requirements of pluggable optics for Ethernet and AI/ML at up to 200G/lane while achieving full electrical and optical plug-and-play.  Specifications will be developed for 200G/lane (DRn and 800G-FR4-500 over 500m) as well as for 100G/lane (30m MMF, DRn, 400G FR4). For more information, contact Jeff Hutchins, Physical and Link Layer Working Group EEI Vice Chair.RTLR project addresses energy efficiency and low latency requirements of pluggable optics for Ethernet and AI/ML scale-out links at up to 200G/lane while achieving full electrical and optical plug-and-play.  Specifications are being developed for 200G/lane (DRn and 800G-FR4-500 over 500m) as well as for 100G/lane (30m MMF, DRn, 400G FR4).   For more information, contact Jeff Hutchins, Physical and Link Layer Working Group EEI Vice Chair.
  • Compute Optics Interface (COI)
    The COI Project is developing energy-efficient, low-latency photonic interfaces to support AI scale-up links utilizing protocols such as PCIe, NVLink, and UALink.  As AI workloads grow requiring larger clusters of local accelerators, high-performance interoperable links are needed for next generation local compute connectivity.  For more information, contact Jeff Hutchins, Physical and Link Layer Working Group Management Co-Vice Chair.

Networking & Operations Working Group/ Network Operator Working Group

  • APIs for Transport SDN
    As the industry looks at Transport Software Defined Networking (SDN), there is a lack of definition for how User Applications interact with Network Applications and Resource Functions. The programmability of Transport SDN requires some of the internal interfaces used by ASON in the past to become open. The expected outcome for this project is a series of Application Program Interface (API) documents addressing: Service Request, Connection Request, Topology, Link Resource Manager, Path Computation, and other APIs identified by the SDN Framework document. For more information on this project contact Jonathan Sadler, Networking Interoperability Working Group Chair.

To contact a Working Group Chair or Vice Chair, please send an email to technicalquestions@oiforum.com