The industry is moving fast – AI, ML and hyperscale demands are pushing interconnect speeds beyond 224Gbps. To drive consensus and accelerate standardization, OIF hosted the 448Gbps Signaling for AI Workshop on April 15-16 in Santa Clara bringing together key industry leaders to address the next-generation challenges of high-speed interconnects. OIF solicited industry proposals to ensure a diverse range of insights and expertise, fostering an open and collaborative exchange of ideas.

Click on the presenter’s name to access their presentation.

Welcome and Opening Remarks
  • Nathan Tracy, President, OIF; Sr Principal Engineer, TE Connectivity
Keynote Speakers
  • Ashwin Gumaste, Principal AI Network Architect, Microsoft
    “On the Considerations Along the Path to 448G for Scale Up and Scale Out AI Workloads”
  • Tad Hofmeister, Optical Hardware Engineer, Machine Learning Systems, Google Cloud
    “A Path to 448Gbps”
  • Xu Wang, Hardware Engineer, Meta Platforms, Inc.
    “An AI System View on 448Gbps Signaling”
  • Sara Zebian, Member of Technical Staff, OpenAI
    “Interconnect Trends for AI Datacenters”
Industry Analysts
  • Lisa Huff, Senior Principal Analyst, Optical Components, Omdia
    “System Architecture Panel and Optical Components Market Update”
  • Alan Weckel, Founder and Technology Analyst, 650 Group
    “Electrical Channel Panel The Road to 448 Gbps SERDES”

SDO Panel moderated by Nathan Tracy
System Architecture Panel moderated by Lisa Huff
  • Dave Ofelt, Sr. Distinguished Engineer, Juniper Networks
    “The 448G Generation from a Network System Vendor’s Perspective”
  • Mark Nowell, Fellow, Cisco
    “System and Rack Design Considerations for 400G”
  • Edo Poleg, Principal Engineer, Toga Networks (A Huawei Company)
    “Building a Switch System Using Next Generation Connectivity”
Electrical Channel Panel moderated by Alan Weckel
  • Mike Peng Li, Fellow, Intel
    “TX/RX, Channel, and Signaling Investigations at 448 Gbps“
  • Andrew Josephson, Sr SI Technologist, Samtec
    “Measurement Results for a 448 Gbps Physical Channel”
  • John Calvin, Sr Strategic Planner, Keysight Technologies
    “Advanced Signal Equalization Methods for 448G”
  • Vivek Shah, Sr. Director, Advanced Technologies, Molex
    “Performance Analysis of Various Modulation Techniques Over 448G Channels”
  • Srinivas Venkataraman, Signal Integrity Engineer, Meta Platforms
    “AI Systems and Interconnects: LR Channel for Scale-up Connectivity”
  • Howard Heck, System Architect, TE Connectivity
    “448G VSR & LR Channels, Challenges, & Trade-offs”
SerDes Panel moderated by Cathy Liu, OIF VP, Broadcom Inc.
  • Kaisheng (Klaus) Hu, Principal SI/PI Engineer, Ciena
    “Overcoming Signal and Power Integrity Bottlenecks in Next-Gen 448G Interconnects”
  • Mike Klempa, Engineer, Alphawave Semi; OIF PLL Interoperability WG Chair
    “Navigating the Path to 448G: Architectural and Ecosystem Considerations Over Electrical Interfaces”
  • Lenin Patra, VP & CTO Platform, Marvell
    “Enabling the 448G SERDES I/O for Scale Up and Scale Out Connectivity for Accelerated Infrastructure”
  • Priyank Shukla, Director of Product Management, Synopsys
    “448G SERDES, Host and Channel Relationships: Intertwined Opportunities and Challenges”
Interconnect and Testing Panel moderated by Tom Issenhuth, OIF MA&E PLL Chair
  • Matt Traverso, Distinguished Engineer, Marvell
    “OIF High-Density Connector Project 448Gbps Considerations”
  • Toshiyasu Ito, Fellow of Engineering, Yamaichi Electronics
    “Connector concept, SI Performance and Routing Length of VLC-PCB for 448Gbps”
  • Paul Brooks, Director of Technical Support, VIAVI Solutions
    “Preparing for 448G Signaling – A Test and Measurement Perspective”
Optical Modulation Panel moderated by Scott Wilkinson
  • Balazs Matuz, Principal Optical Researcher, Huawei Technologies Co., Ltd.
    “448Gb/s Native O/E Modulation Format for AI Compute Networks: PAM4 vs. PAM6”
  • Massimo Sorbara, DMTS Research & Development , Global Foundries
    “Electro-Optical Link Analyses Comparing PAM-4, -6, and -8 at 448 Gb/s Signaling”
Eletrical Panel moderated by Scott Wilkinson
  • Naim Ben-Hamida, Sr. Director, Analog Engineering, Ciena
    “448G Signaling: Trade-offs Between SNR, FEC, and Channel Loss””
  • Curtis Ling, CTO, MaxLinear
    “448G Signaling for AI”
  • Peter Graumann, Technical Fellow, Microchip
    “448G Modulation Proposal”
  • David Stauffer, Sr Director of Architecture, Kandou Bus,
    “400G+ Pathfinding Using Backward-Compatible Orthogonal Signaling”
  • Adam Healey, Fellow, Broadcom Inc.
    “Modulation, Encoding, and Error Correction for 448 Gb/s Per Lane Electrical Links”

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